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usr /
src /
linux-headers-4.15.0-64 /
include /
linux /
[ HOME SHELL ]
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amba
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drwxr-xr-x
avf
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byteorder
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can
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ceph
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clk
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platform_data
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rtc
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soc
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spi
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ssb
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sunrpc
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ulpi
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unaligned
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usb
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uwb
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drwxr-xr-x
wimax
[ DIR ]
drwxr-xr-x
8250_pci.h
1.01
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a.out.h
354
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acct.h
2.49
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acpi.h
37.04
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acpi_dma.h
3.22
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acpi_iort.h
2.15
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acpi_pmtmr.h
674
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adb.h
1.79
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adfs_fs.h
574
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aer.h
1.71
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agp_backend.h
3.45
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agpgart.h
3.82
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ahci-remap.h
607
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ahci_platform.h
1.55
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aio.h
673
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alarmtimer.h
1.83
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altera_jtaguart.h
379
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altera_uart.h
397
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amd-iommu.h
6.78
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amifd.h
1.99
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amifdreg.h
2.65
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anon_inodes.h
494
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apm-emulation.h
1.54
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apm_bios.h
2.68
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apple-gmux.h
1.42
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apple_bl.h
498
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arch_topology.h
840
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arm-cci.h
2.01
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arm-smccc.h
10.54
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arm_sdei.h
2.33
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asn1.h
1.99
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asn1_ber_bytecode.h
2.72
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asn1_decoder.h
675
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assoc_array.h
3.07
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assoc_array_priv.h
5.49
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async.h
1.65
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async_tx.h
6.81
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ata.h
33.18
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ata_platform.h
729
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atalk.h
4.36
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ath9k_platform.h
1.44
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atm.h
287
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atm_suni.h
253
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atm_tcp.h
511
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atmdev.h
10.21
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atmel-mci.h
1.4
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atmel-ssc.h
9.74
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atmel_pdc.h
1.47
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atmel_tc.h
11.33
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atomic.h
30.33
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attribute_container.h
2.47
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audit.h
17.22
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auto_dev-ioctl.h
454
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auto_fs.h
436
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auxvec.h
304
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average.h
2.42
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b1pcmcia.h
666
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backing-dev-defs.h
8.53
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backing-dev.h
13.58
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backlight.h
5.3
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badblocks.h
2.14
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balloon_compaction.h
7.2
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bcd.h
559
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bch.h
2.6
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bcm47xx_nvram.h
1.22
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bcm47xx_sprom.h
600
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bcm47xx_wdt.h
555
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bcm963xx_nvram.h
2.96
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bcm963xx_tag.h
3.6
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bfin_mac.h
559
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binfmts.h
4.77
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bio.h
20.17
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bit_spinlock.h
2.3
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bitfield.h
3.2
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bitmap.h
16.2
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bitops.h
6.61
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bitrev.h
2.53
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bits.h
833
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blk-cgroup.h
22.2
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blk-mq-pci.h
247
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blk-mq-rdma.h
232
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blk-mq-virtio.h
288
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blk-mq.h
9.06
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blk_types.h
9.61
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blkdev.h
58.17
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blkpg.h
436
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blktrace_api.h
3.55
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blockgroup_lock.h
810
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bma150.h
1.89
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bootmem.h
11.7
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bottom_half.h
803
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bpf-cgroup.h
4.53
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bpf.h
18.31
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bpf_trace.h
196
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bpf_types.h
1.88
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bpf_verifier.h
6.71
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brcmphy.h
9.88
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bsearch.h
275
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bsg-lib.h
2.13
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bsg.h
773
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btree-128.h
2.67
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btree-type.h
3.9
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btree.h
6.83
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btrfs.h
145
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buffer_head.h
13.22
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bug.h
1.85
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build_bug.h
3.04
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bvec.h
3.42
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c2port.h
1.49
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cache.h
2.13
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cacheinfo.h
3.7
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capability.h
7.59
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cb710.h
5.69
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cciss_ioctl.h
1.03
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ccp.h
18.24
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cdev.h
845
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cdrom.h
8.75
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cfag12864b.h
2.1
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cgroup-defs.h
25.23
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cgroup.h
25.82
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cgroup_rdma.h
1.33
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cgroup_subsys.h
1.17
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circ_buf.h
1.08
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cleancache.h
3.89
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clk-provider.h
34.29
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clk.h
19.38
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clkdev.h
1.54
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clock_cooling.h
2.06
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clockchips.h
7.27
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clocksource.h
8.31
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cm4000_cs.h
199
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cma.h
1.19
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cmdline-parser.h
1.21
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cn_proc.h
1.85
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cnt32_to_63.h
3.6
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coda.h
2.16
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coda_psdev.h
2.98
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compaction.h
7.1
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compat.h
27.45
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compiler-clang.h
1.31
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compiler-gcc.h
12.33
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compiler-intel.h
1.3
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compiler.h
9.81
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compiler_types.h
7.5
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completion.h
4.05
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component.h
1.37
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concap.h
3.69
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configfs.h
9.22
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connector.h
2.43
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console.h
6.7
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console_struct.h
6.81
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consolemap.h
1.04
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container.h
668
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context_tracking.h
4.43
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context_tracking_state.h
1.39
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cordic.h
1.75
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coredump.h
783
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coresight-pmu.h
1.44
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coresight-stm.h
152
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coresight.h
9.86
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count_zeros.h
1.62
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cper.h
16.11
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cpu.h
6.67
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cpu_cooling.h
3.59
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cpu_pm.h
2.78
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cpu_rmap.h
1.86
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cpufeature.h
1.84
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cpufreq.h
27.93
KB
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cpuhotplug.h
11.98
KB
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cpuidle.h
8.68
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cpumask.h
25.38
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cpuset.h
7.07
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crash_core.h
2.99
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crash_dump.h
2.98
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crc-ccitt.h
369
B
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crc-itu-t.h
613
B
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crc-t10dif.h
415
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crc16.h
622
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crc32.h
2.83
KB
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crc32c.h
293
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crc4.h
192
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crc7.h
316
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crc8.h
3.65
KB
-rw-r--r--
cred.h
12.1
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crypto.h
55.52
KB
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cryptohash.h
319
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cs5535.h
6.28
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ctype.h
1.75
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cuda.h
501
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cyclades.h
10.36
KB
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davinci_emac.h
1.12
KB
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dax.h
3.65
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dca.h
2.63
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dcache.h
18.78
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dccp.h
10.73
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dcookies.h
1.3
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debug_locks.h
1.51
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debugfs.h
10.52
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debugobjects.h
3.89
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delay.h
1.83
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delayacct.h
5.17
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delayed_call.h
709
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dell-led.h
128
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devcoredump.h
2.78
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devfreq-event.h
5.64
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devfreq.h
12.53
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devfreq_cooling.h
3.52
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device-mapper.h
17.83
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device.h
55.43
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device_cgroup.h
1.86
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devpts_fs.h
1.28
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digsig.h
1.35
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dio.h
10.97
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dirent.h
216
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dlm.h
6.01
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dlm_plock.h
678
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dm-dirty-log.h
3.94
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dm-io.h
1.93
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dm-kcopyd.h
2.88
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dm-region-hash.h
3.11
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dm9000.h
1.11
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dma-buf.h
14.7
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dma-contiguous.h
4.48
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dma-debug.h
5.61
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dma-direction.h
338
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dma-fence-array.h
2.49
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dma-fence.h
17.29
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dma-iommu.h
3.62
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dma-mapping.h
24.63
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dma_remapping.h
1.46
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dmaengine.h
45.91
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dmapool.h
1.09
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dmar.h
7.94
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dmi.h
4.08
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dnotify.h
1.02
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dns_resolver.h
1.31
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dqblk_qtree.h
2.19
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dqblk_v1.h
327
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dqblk_v2.h
406
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drbd.h
10.67
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drbd_genl.h
21.49
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drbd_genl_api.h
1.77
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drbd_limits.h
7.82
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ds2782_battery.h
158
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dtlk.h
3.5
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dw_apb_timer.h
1.7
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dynamic_debug.h
5.08
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dynamic_queue_limits.h
3.7
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earlycpio.h
359
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ecryptfs.h
3.82
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edac.h
20.22
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edd.h
1.43
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edma.h
807
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eeprom_93cx6.h
2.94
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eeprom_93xx46.h
776
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efi-bgrt.h
644
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efi.h
47.77
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efs_vh.h
1.55
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eisa.h
2.96
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elevator.h
9.26
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elf-fdpic.h
2.18
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elf-randomize.h
583
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elf.h
1.53
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elfcore-compat.h
1.24
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elfcore.h
2.11
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elfnote.h
3.54
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enclosure.h
4.6
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err.h
1.55
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errno.h
1.34
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errqueue.h
524
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errseq.h
373
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etherdevice.h
15.67
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ethtool.h
17.3
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eventfd.h
2.1
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eventpoll.h
2.16
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evm.h
2.65
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export.h
3.88
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exportfs.h
7.45
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ext2_fs.h
967
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extable.h
999
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extcon-provider.h
4.33
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extcon.h
9.84
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f2fs_fs.h
17.51
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f75375s.h
541
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falloc.h
792
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fanotify.h
245
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fault-inject.h
1.87
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fb.h
28.87
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fbcon.h
281
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fcdevice.h
988
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fcntl.h
1.27
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fd.h
490
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fddidevice.h
1.02
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fdtable.h
3.28
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fec.h
609
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file.h
2.06
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filter.h
26.43
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fips.h
167
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firewire.h
13.4
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firmware-map.h
1.32
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firmware.h
2.34
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fixp-arith.h
4.41
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flat.h
1.61
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flex_array.h
4.31
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flex_proportions.h
2.81
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fmc-sdb.h
1.29
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fmc.h
9.65
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font.h
1.29
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frame.h
813
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freezer.h
8.67
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frontswap.h
2.87
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fs.h
110.29
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fs_enet_pd.h
3.38
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fs_pin.h
619
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fs_stack.h
811
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fs_struct.h
1.03
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fs_uart_pd.h
1.49
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fscache-cache.h
18.4
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fscache.h
27.54
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fscrypt.h
8.93
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fscrypt_notsupp.h
4.45
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fscrypt_supp.h
6.1
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fsi.h
2.37
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fsl-diu-fb.h
4.08
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fsl_devices.h
4.32
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fsl_hypervisor.h
2.76
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fsl_ifc.h
25.06
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fsldma.h
398
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fsnotify.h
7.43
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fsnotify_backend.h
16.66
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ftrace.h
29.86
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ftrace_irq.h
823
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futex.h
1.92
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fwnode.h
4.41
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gameport.h
5.56
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gcd.h
193
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genalloc.h
5.77
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genetlink.h
1.39
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genhd.h
22.73
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genl_magic_func.h
12.05
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genl_magic_struct.h
7.66
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getcpu.h
641
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gfp.h
22.47
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glob.h
256
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goldfish.h
605
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gpio-pxa.h
571
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gpio.h
5.67
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gpio_keys.h
1.63
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hardirq.h
1.95
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hash.h
3
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hashtable.h
6.63
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hdlc.h
3.33
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hdlcdrv.h
6.32
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hdmi.h
9.36
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hid-debug.h
2.07
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hid-roccat.h
688
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hid-sensor-hub.h
9.25
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hid-sensor-ids.h
7.27
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hid.h
34.55
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hiddev.h
2.07
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hidraw.h
1.49
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highmem.h
5.84
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highuid.h
3.12
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hil.h
18.42
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hil_mlc.h
5.13
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hippidevice.h
1.23
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hmm.h
18.19
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host1x.h
9.02
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hp_sdc.h
14.02
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hpet.h
2.55
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hrtimer.h
13.78
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htcpld.h
617
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huge_mm.h
10.1
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hugetlb.h
16.82
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hugetlb_cgroup.h
2.93
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hugetlb_inline.h
374
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hw_breakpoint.h
3.85
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hw_random.h
2.15
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hwmon-sysfs.h
1.98
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hwmon-vid.h
1.48
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hwmon.h
12.07
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hwspinlock.h
11.06
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hyperv.h
38.83
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hypervisor.h
400
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i2c-algo-bit.h
2.24
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i2c-algo-pca.h
2.54
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i2c-algo-pcf.h
1.88
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i2c-dev.h
1.03
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i2c-gpio.h
1.19
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i2c-mux-gpio.h
1.35
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i2c-mux.h
2.29
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i2c-ocores.h
757
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i2c-omap.h
1.21
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i2c-pca-platform.h
441
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i2c-pnx.h
923
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i2c-pxa.h
438
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i2c-smbus.h
1.94
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i2c-xiic.h
1.41
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i2c.h
30.84
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i7300_idle.h
1.95
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i8042.h
2.14
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i8253.h
809
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icmp.h
863
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icmpv6.h
1.29
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ide.h
46.29
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idr.h
7.81
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ieee80211.h
80.94
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ieee802154.h
11.5
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if_arp.h
1.81
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if_bridge.h
2.65
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if_eql.h
1.07
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if_ether.h
1.28
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if_fddi.h
3.44
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if_frad.h
2.87
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if_link.h
554
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if_ltalk.h
188
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if_macvlan.h
2.17
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if_phonet.h
319
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if_pppol2tp.h
727
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if_pppox.h
2.91
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if_tap.h
2.24
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if_team.h
7.65
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if_tun.h
1.14
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if_tunnel.h
409
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if_vlan.h
18.67
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igmp.h
4.15
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ihex.h
1.95
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ima.h
2.53
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imx-media.h
811
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in.h
2.43
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in6.h
1.85
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inet.h
2.8
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inet_diag.h
2.13
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inetdevice.h
8.12
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init.h
9.1
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init_ohci1394_dma.h
196
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init_task.h
7.84
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initrd.h
685
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inotify.h
696
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input-polldev.h
2.17
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input.h
18.81
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integrity.h
1.05
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intel-iommu.h
16.77
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intel-pti.h
1.56
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intel-svm.h
4.96
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interrupt.h
21.15
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interval_tree.h
831
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interval_tree_generic.h
8
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io-64-nonatomic-hi-lo.h
1.14
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io-64-nonatomic-lo-hi.h
1.14
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io-mapping.h
4.32
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io.h
5.76
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ioc3.h
3.14
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ioc4.h
5.78
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iocontext.h
4.74
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iomap.h
3.95
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iommu-common.h
1.41
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iommu-helper.h
950
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iommu.h
21.74
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iopoll.h
5.72
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ioport.h
10.74
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ioprio.h
1.96
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iova.h
7.03
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ip.h
1.07
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ipack.h
8.85
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ipc.h
695
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ipc_namespace.h
4.54
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ipmi-fru.h
3.64
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ipmi.h
11.44
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ipmi_smi.h
8.9
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ipv6.h
8.92
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ipv6_route.h
594
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irq.h
38.05
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irq_cpustat.h
949
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irq_poll.h
575
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irq_sim.h
1.16
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irq_work.h
1.3
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irqbypass.h
3.59
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irqchip.h
1.54
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irqdesc.h
8.15
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irqdomain.h
19.02
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irqflags.h
4.82
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irqhandler.h
362
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irqnr.h
856
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irqreturn.h
503
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isa.h
2.12
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isapnp.h
3.8
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iscsi_boot_sysfs.h
4.09
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iscsi_ibft.h
1.28
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isdn.h
22.99
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isdn_divertif.h
1.27
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isdn_ppp.h
6.64
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isdnif.h
19.26
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isicom.h
1.49
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jbd2.h
46.21
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jhash.h
4.62
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jiffies.h
15.4
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journal-head.h
2.87
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joystick.h
1.28
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jump_label.h
13.32
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jump_label_ratelimit.h
1.12
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jz4740-adc.h
1023
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jz4780-nemc.h
1.16
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kallsyms.h
3.59
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kasan-checks.h
441
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kasan.h
4.48
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kbd_diacr.h
198
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kbd_kern.h
3.84
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kbuild.h
380
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kconfig.h
2.53
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kcore.h
664
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kcov.h
802
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kd.h
211
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kdb.h
7.3
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kdebug.h
487
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kdev_t.h
1.7
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kern_levels.h
1.58
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kernel-page-flags.h
505
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kernel.h
31.25
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kernel_stat.h
2.5
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kernelcapi.h
4.45
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kernfs.h
16.86
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kexec.h
9.64
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key-type.h
6.17
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key.h
12.67
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keyboard.h
665
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kfifo.h
24.81
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kgdb.h
10.7
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khugepaged.h
2.24
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klist.h
1.88
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kmemleak.h
3.86
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kmod.h
1.71
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kmsg_dump.h
2.85
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kobj_map.h
545
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kobject.h
7.62
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kobject_ns.h
1.9
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kprobes.h
14.41
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kref.h
3.28
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ks0108.h
1.57
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ks8842.h
1.19
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ks8851_mll.h
1.04
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ksm.h
2.89
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kthread.h
6.6
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ktime.h
6.71
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kvm_host.h
35.37
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kvm_irqfd.h
2.39
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kvm_para.h
284
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kvm_types.h
1.59
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l2tp.h
261
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lapb.h
1.71
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latencytop.h
1.18
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lcd.h
4.19
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lcm.h
275
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led-class-flash.h
5.42
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led-lm3530.h
3.7
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leds-bd2802.h
642
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leds-lp3944.h
1.07
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leds-lp3952.h
2.5
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leds-pca9532.h
1.01
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leds-regulator.h
1.29
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leds-tca6507.h
1.02
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leds.h
13.67
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leds_pwm.h
407
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libata.h
64.51
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libfdt.h
244
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libfdt_env.h
396
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libgcc.h
1.07
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libnvdimm.h
7.16
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libps2.h
1.75
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license.h
374
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lightnvm.h
10.95
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linkage.h
2.64
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linux_logo.h
2.06
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lis3lv02d.h
5
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list.h
23.3
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list_bl.h
4.19
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list_lru.h
6.29
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list_nulls.h
3.42
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list_sort.h
277
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livepatch.h
6.94
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llc.h
749
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llist.h
9.15
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lockdep.h
18.61
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lockref.h
1.45
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log2.h
5.48
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logic_pio.h
3.18
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lp.h
2.76
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lru_cache.h
12.42
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lsm_audit.h
2.73
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lsm_hooks.h
88.01
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lz4.h
26.44
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lzo.h
1.37
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mISDNdsp.h
1.19
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mISDNhw.h
5.78
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mISDNif.h
14.91
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mailbox_client.h
1.79
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mailbox_controller.h
5.37
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maple.h
2.71
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marvell_phy.h
1.17
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math64.h
6.42
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max17040_battery.h
474
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mbcache.h
1.57
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mbus.h
3.09
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mc146818rtc.h
4.46
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mc6821.h
1.18
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mcb.h
3.88
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mdev.h
4.9
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mdio-bitbang.h
1.18
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mdio-mux.h
1021
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mdio.h
8.89
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mei_cl_bus.h
3.28
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mem_encrypt.h
1.21
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memblock.h
14.6
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memcontrol.h
28.26
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memory.h
4.52
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memory_hotplug.h
10.12
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mempolicy.h
7.44
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mempool.h
2.39
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memremap.h
7.15
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memstick.h
9.73
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mic_bus.h
3.2
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micrel_phy.h
1.42
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microchipphy.h
2.84
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migrate.h
10.02
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migrate_mode.h
758
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mii.h
8.74
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miscdevice.h
2.79
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mm-arch-hooks.h
679
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mm.h
85.2
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mm_inline.h
3.44
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mm_types.h
19.15
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mm_types_task.h
2.4
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mman.h
3.26
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mmdebug.h
1.88
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mmiotrace.h
3.05
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mmu_context.h
378
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mmu_notifier.h
15.84
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mmzone.h
39.68
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mnt_namespace.h
617
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mod_devicetable.h
19.1
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module.h
22.23
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moduleloader.h
2.72
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moduleparam.h
19.42
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mount.h
3.45
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mpage.h
761
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mpi.h
5.17
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mpls.h
394
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mpls_iptunnel.h
178
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mroute.h
4.71
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mroute6.h
3.27
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msdos_fs.h
273
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msg.h
1.02
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msi.h
11.58
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mutex.h
6.91
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mv643xx.h
52.4
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mv643xx_eth.h
1.95
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mv643xx_i2c.h
545
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mvebu-pmsu.h
520
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mxm-wmi.h
1.05
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n_r3964.h
4.06
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namei.h
3.41
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nd.h
5.71
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net.h
11.17
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netdev_features.h
9.39
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netdevice.h
139.26
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netfilter.h
11.74
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netfilter_bridge.h
1.82
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netfilter_defs.h
239
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netfilter_ingress.h
1.44
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netfilter_ipv4.h
424
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netfilter_ipv6.h
1.43
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netlink.h
6.87
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netpoll.h
2.69
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nfs.h
1.31
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nfs3.h
260
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nfs4.h
17.5
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nfs_fs.h
16.03
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nfs_fs_i.h
308
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nfs_fs_sb.h
8.81
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nfs_iostat.h
4.18
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nfs_page.h
5.89
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nfs_xdr.h
38.78
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nfsacl.h
1.15
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nl802154.h
4.23
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nls.h
3.08
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nmi.h
6.56
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node.h
3
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nodemask.h
16.9
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nospec.h
2.14
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notifier.h
7.72
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ns_common.h
235
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nsc_gpio.h
1.42
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nsproxy.h
2.48
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ntb.h
46.52
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ntb_transport.h
3.8
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nubus.h
4.13
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numa.h
292
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nvme-fc-driver.h
38.22
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nvme-fc.h
8.34
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nvme-rdma.h
2.44
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nvme.h
26.61
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nvmem-consumer.h
4.35
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nvmem-provider.h
1.52
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nvram.h
495
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of.h
40.35
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of_address.h
4.47
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of_device.h
3.04
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of_dma.h
2.45
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of_fdt.h
4.19
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of_gpio.h
4.39
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of_graph.h
3.56
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of_iommu.h
1
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of_irq.h
3.6
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of_mdio.h
2.98
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of_net.h
708
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of_pci.h
2.23
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of_pdt.h
1.4
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of_platform.h
4.1
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of_reserved_mem.h
2.35
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oid_registry.h
3.87
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olpc-ec.h
1.08
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omap-dma.h
10.5
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omap-dmaengine.h
583
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omap-gpmc.h
2.22
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omap-iommu.h
520
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omap-mailbox.h
777
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omapfb.h
1.22
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once.h
1.84
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oom.h
3.12
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openvswitch.h
844
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oprofile.h
6.1
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osq_lock.h
1.04
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overflow.h
6.6
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oxu210hp.h
197
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padata.h
6.02
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page-flags-layout.h
2.99
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page-flags.h
23.42
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page-isolation.h
1.9
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page_counter.h
1.46
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page_ext.h
1.89
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page_idle.h
2.62
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page_owner.h
2.3
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page_ref.h
4.99
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pageblock-flags.h
3.28
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pagemap.h
18.92
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pagevec.h
2.3
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parman.h
2.87
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parport.h
17.84
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parport_pc.h
6.56
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parser.h
1.04
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pata_arasan_cf_data.h
1.22
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patchkey.h
757
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path.h
572
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pch_dma.h
999
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pci-acpi.h
3.44
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pci-aspm.h
882
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pci-ats.h
1.39
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pci-dma-compat.h
4.41
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pci-dma.h
454
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pci-ecam.h
2.54
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pci-ep-cfs.h
1.09
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pci-epc.h
5.26
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pci-epf.h
4.83
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pci.h
81.38
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pci_hotplug.h
6.91
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pci_ids.h
119.4
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pcieport_if.h
2.35
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pda_power.h
1.12
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pe.h
15.6
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percpu-defs.h
18.17
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percpu-refcount.h
9.93
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percpu-rwsem.h
4.09
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percpu.h
5.02
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percpu_counter.h
4.26
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percpu_ida.h
2.32
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perf_event.h
38.74
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perf_regs.h
1.02
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personality.h
393
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pfn.h
666
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pfn_t.h
3.23
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phonet.h
1.12
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phy.h
31
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phy_fixed.h
1.64
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phy_led_triggers.h
1.46
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phylink.h
5.06
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pid.h
5.77
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pid_namespace.h
2.33
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pim.h
2.67
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pipe_fs_i.h
6.46
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pkeys.h
916
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pktcdvd.h
5.87
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pl320-ipc.h
758
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platform_device.h
12.43
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plist.h
8.69
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pm-trace.h
940
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pm.h
34.21
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pm2301_charger.h
1.68
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pm_clock.h
2.45
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pm_domain.h
9.03
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pm_opp.h
10.08
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pm_qos.h
8.51
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pm_runtime.h
8.52
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pm_wakeirq.h
1.31
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pm_wakeup.h
6.61
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pmbus.h
1.58
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pmu.h
2.34
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pnfs_osd_xdr.h
9.27
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pnp.h
15.4
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poison.h
2.66
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poll.h
3.19
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posix-clock.h
4.41
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posix-timers.h
3.55
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posix_acl.h
3.06
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posix_acl_xattr.h
1.58
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power_supply.h
13.41
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powercap.h
12.59
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ppp-comp.h
3.1
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ppp_channel.h
3.07
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ppp_defs.h
454
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pps-gpio.h
1.01
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pps_kernel.h
3.55
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pr.h
566
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preempt.h
9.33
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prefetch.h
1.54
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prime_numbers.h
1.35
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printk.h
15.24
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proc_fs.h
3.26
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proc_ns.h
2.44
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processor.h
2.14
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profile.h
2.68
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projid.h
2.34
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property.h
9.79
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psci.h
1.87
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pstore.h
7.58
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pstore_ram.h
2.89
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pti.h
240
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ptp_classify.h
2.89
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ptp_clock_kernel.h
8.39
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ptr_ring.h
16.29
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ptrace.h
14.77
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purgatory.h
589
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pvclock_gtod.h
548
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pwm.h
16.8
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pwm_backlight.h
740
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pxa168_eth.h
728
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pxa2xx_ssp.h
9.8
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qcom_scm.h
4.09
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qnx6_fs.h
3.27
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quicklist.h
2.13
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quota.h
18.86
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quotaops.h
10.02
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radix-tree.h
21.77
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raid_class.h
2.08
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ramfs.h
762
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random.h
5.07
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range.h
651
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ras.h
1.18
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ratelimit.h
2.63
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rational.h
639
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rbtree.h
5.36
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rbtree_augmented.h
8.67
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rbtree_latch.h
6.62
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rcu_node_tree.h
4.34
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rcu_segcblist.h
3.26
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rcu_sync.h
2.57
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rculist.h
23.53
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rculist_bl.h
4.36
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rculist_nulls.h
4.93
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rcupdate.h
32.58
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rcupdate_wait.h
1.63
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rcutiny.h
3.64
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rcutree.h
3.56
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rcuwait.h
1.82
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reboot-mode.h
600
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reboot.h
2.05
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reciprocal_div.h
1.01
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refcount.h
2.6
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regmap.h
42.34
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regset.h
15.08
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relay.h
8.84
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remoteproc.h
18.48
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reservation.h
8.12
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reset-controller.h
2.12
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reset.h
13.69
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resource.h
339
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resource_ext.h
2.22
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restart_block.h
1.11
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rfkill.h
9.89
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rhashtable.h
38.24
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ring_buffer.h
6.79
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rio.h
19.23
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rio_drv.h
14.71
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rio_ids.h
1.29
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rio_regs.h
19.27
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rmap.h
8.76
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rmi.h
12.13
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rndis.h
16.86
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rodata_test.h
559
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root_dev.h
579
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rpmsg.h
8.38
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rslib.h
2.99
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rtc.h
8.71
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rtmutex.h
3.47
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rtnetlink.h
4.27
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rtsx_common.h
1.44
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rtsx_pci.h
40.14
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rtsx_usb.h
15.95
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rwlock.h
4.35
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rwlock_api_smp.h
7.67
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rwlock_types.h
1.12
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rwsem-spinlock.h
1.58
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rwsem.h
6
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s3c_adc_battery.h
971
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sa11x0-dma.h
572
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sbitmap.h
13.56
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scatterlist.h
12.9
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scc.h
2.84
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sched.h
47.53
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sched_clock.h
661
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scif.h
58.85
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scpi_protocol.h
2.58
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screen_info.h
191
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sctp.h
21.92
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scx200.h
1.82
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scx200_gpio.h
2.38
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sdb.h
4.17
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sdla.h
6.9
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seccomp.h
2.66
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securebits.h
239
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security.h
47.85
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sed-opal.h
1.94
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seg6.h
121
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seg6_genl.h
136
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seg6_hmac.h
136
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seg6_iptunnel.h
148
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seg6_local.h
100
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selection.h
1.39
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selinux.h
910
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sem.h
2.02
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semaphore.h
1.36
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seq_buf.h
3.16
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seq_file.h
6.68
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seq_file_net.h
713
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seqlock.h
16
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seqno-fence.h
3.96
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serdev.h
9.48
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serial.h
630
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serial_8250.h
5.91
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serial_bcm63xx.h
4.73
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serial_core.h
16.38
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serial_max3100.h
1.39
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serial_pnx8xxx.h
2.61
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serial_s3c.h
9.24
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serial_sci.h
1.57
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serio.h
4.42
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set_memory.h
740
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sfi.h
5.75
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sfi_acpi.h
3.39
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sfp.h
10.4
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sh_clk.h
5.96
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sh_dma.h
3.61
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sh_eth.h
417
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sh_intc.h
3.42
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sh_timer.h
172
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shdma-base.h
4.41
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shm.h
1.56
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shmem_fs.h
5.33
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shrinker.h
2.82
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signal.h
12.22
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Code Editor : clk-provider.h
/* * linux/include/linux/clk-provider.h * * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H #include <linux/io.h> #include <linux/of.h> #ifdef CONFIG_COMMON_CLK /* * flags used across common struct clk. these flags should only affect the * top-level framework. custom flags for dealing with hardware specifics * belong in struct clk_foo */ #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ /* unused */ #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) struct clk; struct clk_hw; struct clk_core; struct dentry; /** * struct clk_rate_request - Structure encoding the clk constraints that * a clock user might require. * * @rate: Requested clock rate. This field will be adjusted by * clock drivers according to hardware capabilities. * @min_rate: Minimum rate imposed by clk users. * @max_rate: Maximum rate imposed by clk users. * @best_parent_rate: The best parent rate a parent can provide to fulfill the * requested constraints. * @best_parent_hw: The most appropriate parent clock that fulfills the * requested constraints. * */ struct clk_rate_request { unsigned long rate; unsigned long min_rate; unsigned long max_rate; unsigned long best_parent_rate; struct clk_hw *best_parent_hw; }; /** * struct clk_ops - Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * * @prepare: Prepare the clock for enabling. This must not return until * the clock is fully prepared, and it's safe to call clk_enable. * This callback is intended to allow clock implementations to * do any initialisation that may sleep. Called with * prepare_lock held. * * @unprepare: Release the clock from its prepared state. This will typically * undo any work done in the @prepare callback. Called with * prepare_lock held. * * @is_prepared: Queries the hardware to determine if the clock is prepared. * This function is allowed to sleep. Optional, if this op is not * set then the prepare count will be used. * * @unprepare_unused: Unprepare the clock atomically. Only called from * clk_disable_unused for prepare clocks with special needs. * Called with prepare mutex held. This function may sleep. * * @enable: Enable the clock atomically. This must not return until the * clock is generating a valid clock signal, usable by consumer * devices. Called with enable_lock held. This function must not * sleep. * * @disable: Disable the clock atomically. Called with enable_lock held. * This function must not sleep. * * @is_enabled: Queries the hardware to determine if the clock is enabled. * This function must not sleep. Optional, if this op is not * set then the enable count will be used. * * @disable_unused: Disable the clock atomically. Only called from * clk_disable_unused for gate clocks with special needs. * Called with enable_lock held. This function must not * sleep. * * @recalc_rate Recalculate the rate of this clock, by querying hardware. The * parent rate is an input parameter. It is up to the caller to * ensure that the prepare_mutex is held across this call. * Returns the calculated rate. Optional, but recommended - if * this op is not set then clock rate will be initialized to 0. * * @round_rate: Given a target rate as input, returns the closest rate actually * supported by the clock. The parent rate is an input/output * parameter. * * @determine_rate: Given a target rate as input, returns the closest rate * actually supported by the clock, and optionally the parent clock * that should be used to provide the clock rate. * * @set_parent: Change the input source of this clock; for clocks with multiple * possible parents specify a new parent by passing in the index * as a u8 corresponding to the parent in either the .parent_names * or .parents arrays. This function in affect translates an * array index into the value programmed into the hardware. * Returns 0 on success, -EERROR otherwise. * * @get_parent: Queries the hardware to determine the parent of a clock. The * return value is a u8 which specifies the index corresponding to * the parent clock. This index can be applied to either the * .parent_names or .parents arrays. In short, this function * translates the parent value read from hardware into an array * index. Currently only called when the clock is initialized by * __clk_init. This callback is mandatory for clocks with * multiple parents. It is optional (and unnecessary) for clocks * with 0 or 1 parents. * * @set_rate: Change the rate of this clock. The requested rate is specified * by the second argument, which should typically be the return * of .round_rate call. The third argument gives the parent rate * which is likely helpful for most .set_rate implementation. * Returns 0 on success, -EERROR otherwise. * * @set_rate_and_parent: Change the rate and the parent of this clock. The * requested rate is specified by the second argument, which * should typically be the return of .round_rate call. The * third argument gives the parent rate which is likely helpful * for most .set_rate_and_parent implementation. The fourth * argument gives the parent index. This callback is optional (and * unnecessary) for clocks with 0 or 1 parents as well as * for clocks that can tolerate switching the rate and the parent * separately via calls to .set_parent and .set_rate. * Returns 0 on success, -EERROR otherwise. * * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy * is expressed in ppb (parts per billion). The parent accuracy is * an input parameter. * Returns the calculated accuracy. Optional - if this op is not * set then clock accuracy will be initialized to parent accuracy * or 0 (perfect clock) if clock has no parent. * * @get_phase: Queries the hardware to get the current phase of a clock. * Returned values are 0-359 degrees on success, negative * error codes on failure. * * @set_phase: Shift the phase this clock signal in degrees specified * by the second argument. Valid values for degrees are * 0-359. Return 0 on success, otherwise -EERROR. * * @init: Perform platform-specific initialization magic. * This is not not used by any of the basic clock types. * Please consider other ways of solving initialization problems * before using this callback, as its use is discouraged. * * @debug_init: Set up type-specific debugfs entries for this clock. This * is called once, after the debugfs directory entry for this * clock has been created. The dentry pointer representing that * directory is provided as an argument. Called with * prepare_lock held. Returns 0 on success, -EERROR otherwise. * * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts. If enabling a clock requires code that might sleep, * this must be done in clk_prepare. Clock enable code that will never be * called in a sleepable context may be implemented in clk_enable. * * Typically, drivers will call clk_prepare when a clock may be needed later * (eg. when a device is opened), and clk_enable when the clock is actually * required (eg. from an interrupt). Note that clk_prepare MUST have been * called before clk_enable. */ struct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); int (*is_prepared)(struct clk_hw *hw); void (*unprepare_unused)(struct clk_hw *hw); int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); int (*get_phase)(struct clk_hw *hw); int (*set_phase)(struct clk_hw *hw, int degrees); void (*init)(struct clk_hw *hw); int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); }; /** * struct clk_init_data - holds init data that's common to all clocks and is * shared between the clock provider and the common clock framework. * * @name: clock name * @ops: operations this clock supports * @parent_names: array of string names for all possible parents * @num_parents: number of possible parents * @flags: framework-level hints and quirks */ struct clk_init_data { const char *name; const struct clk_ops *ops; const char * const *parent_names; u8 num_parents; unsigned long flags; }; /** * struct clk_hw - handle for traversing from a struct clk to its corresponding * hardware-specific structure. struct clk_hw should be declared within struct * clk_foo and then referenced by the struct clk instance that uses struct * clk_foo's clk_ops * * @core: pointer to the struct clk_core instance that points back to this * struct clk_hw instance * * @clk: pointer to the per-user struct clk instance that can be used to call * into the clk API * * @init: pointer to struct clk_init_data that contains the init data shared * with the common clock framework. */ struct clk_hw { struct clk_core *core; struct clk *clk; const struct clk_init_data *init; }; /* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw: handle between common and hardware-specific interfaces * @fixed_rate: constant frequency of clock */ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; unsigned long fixed_accuracy; u8 flags; }; #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_unregister_fixed_rate(struct clk *clk); struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); /** * struct clk_gate - gating clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling gate * @bit_idx: single bit controlling gate * @flags: hardware-specific flags * @lock: register lock * * Clock which can gate its output. Implements .enable & .disable * * Flags: * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; u8 flags; spinlock_t *lock; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); struct clk_div_table { unsigned int val; unsigned int div; }; /** * struct clk_divider - adjustable divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements * .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is * the raw value read from the register, with the value of zero considered * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from * the hardware register * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit * of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded * to the closest integer instead of the up one. * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should * not be changed by the clock framework. * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; const struct clk_div_table *table; spinlock_t *lock; }; #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) #define CLK_DIVIDER_HIWORD_MASK BIT(3) #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *clk_hw_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); /** * struct clk_mux - multiplexer clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer * @shift: shift to multiplexer bit field * @width: width of mutliplexer bit field * @flags: hardware-specific flags * @lock: register lock * * Clock with multiple selectable parents. Implements .get_parent, .set_parent * and .recalc_rate * * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this * register, and mask of mux bits are in higher 16-bit of this register. * While setting the mux bits, higher 16-bit should also be updated to * indicate changing mux bits. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. */ struct clk_mux { struct clk_hw hw; void __iomem *reg; u32 *table; u32 mask; u8 shift; u8 flags; spinlock_t *lock; }; #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) #define CLK_MUX_HIWORD_MASK BIT(2) #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops; struct clk *clk_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); void clk_unregister_mux(struct clk *clk); void clk_hw_unregister_mux(struct clk_hw *hw); void of_fixed_factor_clk_setup(struct device_node *node); /** * struct clk_fixed_factor - fixed multiplier and divider clock * * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. * Implements .recalc_rate, .set_rate and .round_rate */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; }; #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) extern const struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); /** * struct clk_fractional_divider - adjustable fractional divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @mshift: shift to the numerator bit field * @mwidth: width of the numerator bit field * @nshift: shift to the denominator bit field * @nwidth: width of the denominator bit field * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. */ struct clk_fractional_divider { struct clk_hw hw; void __iomem *reg; u8 mshift; u8 mwidth; u32 mmask; u8 nshift; u8 nwidth; u32 nmask; u8 flags; void (*approximation)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m, unsigned long *n); spinlock_t *lock; }; #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); void clk_hw_unregister_fractional_divider(struct clk_hw *hw); /** * struct clk_multiplier - adjustable multiplier clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the multiplier * @shift: shift to the multiplier bit field * @width: width of the multiplier bit field * @lock: register lock * * Clock with an adjustable multiplier affecting its output frequency. * Implements .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read * from the register, with 0 being a valid value effectively * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is * set, then a null multiplier will be considered as a bypass, * leaving the parent rate unmodified. * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be * rounded to the closest integer instead of the down one. */ struct clk_multiplier { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; spinlock_t *lock; }; #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) extern const struct clk_ops clk_multiplier_ops; /*** * struct clk_composite - aggregate clock of mux, divider and gate clocks * * @hw: handle between common and hardware-specific interfaces * @mux_hw: handle between composite and hardware-specific mux clock * @rate_hw: handle between composite and hardware-specific rate clock * @gate_hw: handle between composite and hardware-specific gate clock * @mux_ops: clock ops for mux * @rate_ops: clock ops for rate * @gate_ops: clock ops for gate */ struct clk_composite { struct clk_hw hw; struct clk_ops ops; struct clk_hw *mux_hw; struct clk_hw *rate_hw; struct clk_hw *gate_hw; const struct clk_ops *mux_ops; const struct clk_ops *rate_ops; const struct clk_ops *gate_ops; }; #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) struct clk *clk_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_unregister_composite(struct clk *clk); struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_hw_unregister_composite(struct clk_hw *hw); /*** * struct clk_gpio_gate - gpio gated clock * * @hw: handle between common and hardware-specific interfaces * @gpiod: gpio descriptor * * Clock with a gpio control for enabling and disabling the parent clock. * Implements .enable, .disable and .is_enabled */ struct clk_gpio { struct clk_hw hw; struct gpio_desc *gpiod; }; #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) extern const struct clk_ops clk_gpio_gate_ops; struct clk *clk_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, struct gpio_desc *gpiod, unsigned long flags); struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, struct gpio_desc *gpiod, unsigned long flags); void clk_hw_unregister_gpio_gate(struct clk_hw *hw); /** * struct clk_gpio_mux - gpio controlled clock multiplexer * * @hw: see struct clk_gpio * @gpiod: gpio descriptor to select the parent of this clock multiplexer * * Clock with a gpio control for selecting the parent clock. * Implements .get_parent, .set_parent and .determine_rate */ extern const struct clk_ops clk_gpio_mux_ops; struct clk *clk_register_gpio_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, unsigned long flags); struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, unsigned long flags); void clk_hw_unregister_gpio_mux(struct clk_hw *hw); /** * clk_register - allocate a new clock, register it and return an opaque cookie * @dev: device that is registering this clock * @hw: link to hardware-specific clock data * * clk_register is the primary interface for populating the clock tree with new * clock nodes. It returns a pointer to the newly allocated struct clk which * cannot be dereferenced by driver code but may be used in conjuction with the * rest of the clock API. In the event of an error clk_register will return an * error code; drivers must test for an error code after calling clk_register. */ struct clk *clk_register(struct device *dev, struct clk_hw *hw); struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); void clk_unregister(struct clk *clk); void devm_clk_unregister(struct device *dev, struct clk *clk); void clk_hw_unregister(struct clk_hw *hw); void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); /* helper functions */ const char *__clk_get_name(const struct clk *clk); const char *clk_hw_get_name(const struct clk_hw *hw); struct clk_hw *__clk_get_hw(struct clk *clk); unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long __clk_get_flags(struct clk *clk); unsigned long clk_hw_get_flags(const struct clk_hw *hw); #define clk_hw_can_set_rate_parent(hw) \ (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) bool clk_hw_is_prepared(const struct clk_hw *hw); bool clk_hw_is_enabled(const struct clk_hw *hw); bool __clk_is_enabled(struct clk *clk); struct clk *__clk_lookup(const char *name); int __clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); int __clk_mux_determine_rate_closest(struct clk_hw *hw, struct clk_rate_request *req); int clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req, unsigned long flags); void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { dst->clk = src->clk; dst->core = src->core; } static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags) { return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags); } /* * FIXME clock api without lock protection */ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); struct of_device_id; typedef void (*of_clk_init_cb_t)(struct device_node *); struct clk_onecell_data { struct clk **clks; unsigned int clk_num; }; struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; extern struct of_device_id __clk_of_table; #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) /* * Use this macro when you have a driver that requires two initialization * routines, one at of_clk_init(), and one at platform device probe */ #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ static void __init name##_of_clk_init_driver(struct device_node *np) \ { \ of_node_clear_flag(np, OF_POPULATED); \ fn(np); \ } \ OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) #ifdef CONFIG_OF int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data); int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); void of_clk_del_provider(struct device_node *np); void devm_of_clk_del_provider(struct device *dev); struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data); struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data); unsigned int of_clk_get_parent_count(struct device_node *np); int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size); const char *of_clk_get_parent_name(struct device_node *np, int index); int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags); void of_clk_init(const struct of_device_id *matches); #else /* !CONFIG_OF */ static inline int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data) { return 0; } static inline int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline void of_clk_del_provider(struct device_node *np) {} static inline void devm_of_clk_del_provider(struct device *dev) {} static inline struct clk *of_clk_src_simple_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk *of_clk_src_onecell_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline unsigned int of_clk_get_parent_count(struct device_node *np) { return 0; } static inline int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size) { return 0; } static inline const char *of_clk_get_parent_name(struct device_node *np, int index) { return NULL; } static inline int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags) { return 0; } static inline void of_clk_init(const struct of_device_id *matches) {} #endif /* CONFIG_OF */ /* * wrap access to peripherals in accessor routines * for improved portability across platforms */ #if IS_ENABLED(CONFIG_PPC) static inline u32 clk_readl(u32 __iomem *reg) { return ioread32be(reg); } static inline void clk_writel(u32 val, u32 __iomem *reg) { iowrite32be(val, reg); } #else /* platform dependent I/O accessors */ static inline u32 clk_readl(u32 __iomem *reg) { return readl(reg); } static inline void clk_writel(u32 val, u32 __iomem *reg) { writel(val, reg); } #endif /* platform dependent I/O accessors */ #ifdef CONFIG_DEBUG_FS struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, void *data, const struct file_operations *fops); #endif #endif /* CONFIG_COMMON_CLK */ #endif /* CLK_PROVIDER_H */
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